New Paltz sign

Division of Engineering Programs
State University of New York - New Paltz

Baback A. Izadi, Ph.D.

Email: bai@engr.newpaltz.edu
Phone: (845) 257 - 3823
FAX : (845) 257 - 3730

Course Title: Digital Logic Fundamentals
Course Number:
EGC220
Credit: 3
Prerequisite: MAT251
Corequisite: EGC221

 

Spring 2018

Meeting Days: Monday - Thursday
Meeting Time:

  • 9:30 AM - 10:45 AM

Meeting Room: Wooster Hall 221

 

Syllabus

Teaching Assistant

Bullet Yashaswini Reddy
Bullet barlay1@hawkmail.newpaltz.edu (845) 546-5362

 

Textbook:

 "Digital Design," online textbook by ZyBooks (all students enrolled in the class has access to it and will be used partially for assignments). The cost to subscribe is $48 and it will be valid through 1/7/2017. To get access:

  1. Sign up at zyBooks.com:
  2. Enter zyBook code NEWPALTZEGC220IzadiSpring2018
  3. Click Subcribe
  4. Choose the appropriate section

Activities prior to each lecture:

Lecture Date

Lecture Note

Watch Lecture Video
on Blackboard

Additional Activity

Lecture Notes
1/22/2018 Syllabus      

1/25/2018

1-Number systems

Lectures 1 & 2

Read text Chaper 1, Try Problems 1

Class Notes 1/25/18

1/29/2018

1-Number systems

Lectures 3 & 4

Read text Chaper 1, Try Problems 2

Class Notes 1/29/18

2/1/2018

1-Number systems

Lectures 5 &6

Read text Chaper 1, Try Problems 3

Class Notes 2/1/18

2/5/2018

2 - Boolean Logic

Lectures 7 & 8

Read text Chapter 2,  see sample operations, Try Problem 4

Class Notes 2/5/18

2/8/2018

3 - Boolean Logic Functions

Lectures 9 & 10

Read text Chapter 2, Try Problem 5

Class Notes 2/8/2018

2/12/2018

3 - Boolean Logic Functions

Lectures 11 & 12

Read text Chapter 2, Try Problem 6

Class Notes 2/12/2018

2/15/2018

3 - Boolean Logic Functions

Lectures 13 & 14

Read text Chapter 2,Try Problem 7

Class Notes 2/15/2018

2/22/2018

4-Simplification Using K-Map

Lectures 15 & 16

Read Text Chapter 3,Try Problem 8

Class Notes 2/22/2018

2/26/2018

4-Simplification Using K-Map

Lectures 17 & 18

Read Text Chapter 3,Try Problem 9

 

3/1/2018

5-Design of Combinational Circuits

Lectures 19 & 20

Read Text Chapter 3,Try Problem 10

 

3/5/2018

Test 1

 

Practice Problems

 

3/8/2018

5-Design of Combinational Circuits

Lectures 21& 22

Read Text Chapter 3, Try Problem 11

 

3/12/2018

Design of Decoders

Lectures 23 & 24

Read Text Chapter 3, Try Problem 12

 

3/15/2018

Design of Encoder / Mux/ DeMux

Lectures 25 & 26

Read Text Chapter 3, Try Problem 13

 

3/26/2018

6- Programmable Logic Devices

Lectures 27 & 28

Try Problem 14

 

3/29/2018

7- Design Using Verilog

Lectures 29 & 30

Read Text Chapter 4, Try Problem 15

 

4/2/2018

7- Design Using Verilog
8- Latches

Lectures 31 & 32

Read Text Chapter 5, Try Problem 16

 

4/5/2018

8- Flip-flops and Ripple Counters

Lectures 33 & 34

Read text Chaper 5 & Try Problem 17

 

4/9/2018

8- Asynchronous and Synchronous Circuits

Lectures 35 & 36

Read text Chaper 5 & Try Problem 18

 

4/12/2018

8- Analysis of Sequential Circuits

Lectures 37 & 38

Read text Chaper 5 & Try Problem 19

 

4/16/2018

Test 2

 

Practice Problems

 

4/19/2018

8- Design of Sequential Circuits

Lectures 39 & 40

Read Text Chapter 5, Try Problem 20

 

4/23/2018

8- Sequential Circuits

 

Read Text Chapter 5, Try Problem 20

 

4/26/2018

8- Verilog in Sequential Circuits 

Lectures 41 & 42

Read Text Chapter 5, Try Problem 21 

 

4/30/2018

8- Design of Finite State Machine

Lectures 43 & 44

Try Problem 22

 

5/3/2018

8- Design of a Controller

Lectures 45

Read Text Chapter 5, Try Problem 23 

 

5/7/2018

Review

 

 

 
5/14/2018 Final Exam 10:15 AM - 12:15 PM      

 

Homework Assignments

Homework Number
Due Date
Solution
HW #1 2/15/2018  
HW #2 3/1/2018  
     
     
     
     
     

ZyBook Activity Assignments:

ZyBook activity
Due Date
Do Chapter 1 problems 2/16/2018
Do Problem set 2 3/2/2018

Tests:

Tests
Date

Quiz_Keys

Lecture Notes:

Bullet 1 Number Systems
Bullet 2 Boolean Logic
Bullet 3 Boolean Logic Functions
Bullet 4 Simplification Using K-Map
Bullet 5 Design of Combinational Circuits
Bullet 6 Programmable Logic Devices
Bullet 7 Design Using Verilog
Bullet 8 Sequential Circuits
Bullet 9 Sequential Circuits II
Bullet 10 Design Using Verilog II

 

Tutorials:

BulletIntroduction to Verilog
BulletTutorial on Quartus II Schematic Capture
BulletTutorial on Quartus II Verilog
BulletTutorial on using DE-series boards
BulletDE-series boards manual
BulletPin assignment for DE-series boards

BulletYoutube Quartus II Tutorial Designing a simple Circuit

BulletYoutube Creating a Waveform Simulation for Altera Quartus
BulletYoutube Quartus II Tutorial
 

 

Relevant Web Sites

Bullet Digital Logic Fundamentals
Bullet Digital logic tutorial
Bullet Combinational Logic Tutorial
Bullet

Texas Instruments Digital Logic Families

Bullet Biography of George Boole

 

Handouts

bullet Some basic hints and suggestion on breadboarding
bullet Digital Symbols (you may download it for your lab reports and homeworks)
 
bullet PLD Symbol
Bullet Chapter two class notes
Bullet Chapter three class notes
Bullet Chapter four class notes
Bullet Kmap

Additional practice problems

 


Last updated on Thursday, February 22, 2018 1:56 PM
 
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