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The major objective of this
workshop is to emphasize low power aspects with particular regard to design,
architecture, tools and technologies. The workshop seeks original contributions
on, but not limited to, the following topics:
- Logic and Circuit Design
-- Low voltage low power logic families, Low power circuits, Memory
circuits, Low power arithmetic and signal processing circuits, Asynchronous
and self-timed circuits, Adiabatic switching.
- Microarchitecture Design
-- Processor core design, Cache design, Pipelining, Bus encoding.
- System Design -- Microprocessor,
DSP and embedded systems design, ASIC and FPGA designs, Power aware
compiler and operating system design, Application level optimizations,
Voltage and instruction scheduling.
- Physical Design --
Library optimization and characterization, Power analysis, IR drop analysis,
Power models, Power supply and delivery, Power topology design.
- Testing and Characterization
-- Low VT low voltage process, SOI, IDDQ, Models and parameter extraction.
- Low Power EDA Tools
-- Energy simulation and estimation tools, RTL/gate-level simulation
based power analysis, Low power synthesis, RTL exploration, RTL/gate-level
optimization, Low power clock tree synthesis, Interconnect modeling,
Behavioral and system level design aids, and Algorithmic level tools.
- Technologies -- Emerging
logic and memory technologies, Cooling technologies, Battery technologies.
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