Building low power VLSI systems has emerged as a significant performance goal due to the demand for high integration density and the vast growth in portable electronic systems such as laptop and notebook computers and hand-held communication devices. In CMOS designs a better means of achieving this is by reducing the dynamic power dissipation. The use of pass networks in CMOS designs has shown a reduction in power consumption to a large extent. In this regard, various research activities are being pursued in low power design.
· Formal techniques for evaluating pass
network switching activity
· Library cells using pass logic