In this experiment the student will design and implement a ripple counter using EWB.
Procedure:
Using J-K flip-flops and a gate, design a ripple counter that counts from 5 to 42. Your
gate may not have more than 4 inputs. Using logic analyzer verify the operation of your
circuit. Connect your outputs to seven segment displays. Have your lab signed off.
Using D flip-flops and a gate, design a ripple counter that counts from 42 to 6. Your
gate may not have more than 4 inputs. Using logic analyzer verify the operation of your
circuit. Connect your outputs to seven segment displays. Have your lab signed off.