A parity circuit provides a means of detecting possible loss of data during data transfer. It accomplishes this by adding a parity bit ( a "one" or "zero") to the data message and transmitting the data and parity to the receiver. The generator parity bit becomes a part of the transmitted message.

If the transmitted parity bit does not agree with the parity scheme used (odd or even parity), as checked by the parity checker circuit, transmission is halted because the probability is extremely high a message bit has been dropped, lost or missing.

Procedure

1. Using EWB, design and implement the following circuits.

1. A four bit message even parity generator.
2. A four bit message even parity checker

2. Implement your design using a Signetics 16L8 PAL chip. The pin-out of the chip is in the Programmable Logic Devices handout which was distributed in the lecture.
3. Have your circuits signed by your professor or TA.