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Department of Electrical &
Computer Engineering

Baback Izadi

 

Email: bai@engr.newpaltz.edu
Phone: (845) 257 - 3823
FAX : (845) 257 - 3730

Digital Logic Lab
Course Number: EGC208
Credit: 1
Co-requisite: EGC230

home
office hours
teaching
useful links

Fall 2013

Meeting Days: Wednesday
Meeting Time: 10:50 AM- 1:30 PM
Meeting Room: REH211

Syllabus

Teaching Assistant

Bullet
TBD

 

Lab report template

Lab number
Title
Due date
1
9/4/2013
2
9/11/2013
3
9/18/2013
4
9/25/2013
5

Design of a Multiplexer/Demultiplexer

10/2/2013
6
10/9/2013
7
10/16/2013
8
10/30/2013
9
11/13/2013
10
11/20/2013
11
12/4/2013

Oral Project Presentation: 12/4/2013

Tutorials:

Bullet Tutorial to simulate and verify the design using VHDL
Bullet Tutorial to simulate and verify the design using Verilog
Bullet Tutorial to Download to FPGA Board
Bullet Xilinx Verilog Tutorial
Bullet Xilinx VHDL Tutorial
Bullet ModelSim Tutorial
Bullet Tutorial on Sequential Logic Design
Bullet Xilinx State Editor Tutorial
Bullet Additional Verilog Tutorial

Relevant Web Sites

Bullet Digital Logic Fundamentals
Bullet Digital logic tutorial
Bullet Combinational Logic Tutorial
Bullet Latches and Flip flops
Bullet Xilinx:     http://www.xilinx.com/programs/xds1.htm
Bullet

Texas Instruments Digital Logic Families

Bullet Go here if you need software to view and print Postscript files
Bullet Go here if you need software to view and print PDF files under Windows
Bullet Biography of George Boole
Bullet To download a demo version of  Electronic Workbench click on http://www.interactiv.com/html/demo.html
Bullet

Tutorial on ISE at
http://www.xilinx.com/support/training/north-america-home-page.htm

Handouts

 

bullet Some basic hints and suggestion on breadboarding
bullet Detail of Digilab boards
bullet Digital Symbols (you may download it for your lab reports and homeworks)
bullet General Guideline to Final Lab Presentation
bullet General Presentation Guidelines
   
   

Last updated on Tuesday, November 12, 2013 7:11 PM