ISE State Editor Tutorial
Objective
This tutorial will give you exposure to using StateCAD and VHDL. In addition, you will also be again using HDL Bencher and Modelsim for simulating the functional design. Finally, you will download the design to the Spartan-XL board to visually verify the design.
This tutorial shows you how to create, using StateCAD and VHDL, a simple sequence generator (Table 1 & Figure 1):
Table 1 - Sequence Generator State Table
Figure 1 - Sequence
Generator State Diagram
The state diagram generates two distinct sequences based on the values of MODE and RESET. When RESET is high, the design is reset back to the first state, State0. When MODE is high, the sequence toggles between State0 and State1. However, when MODE is low, the sequence is State0->State2->State1->State3->State0 and so on. The outputs of this Mealy machine are a 2-bit binary encoding of the states, from 0 to 3, and are assigned on the transition from one state to another.
Step 1 - Starting ISE and Opening a New Project
To start the Xilinx ISE tools, click on the Start->Programs->Xilinx Foundation Series ISE x.xi->Project Manager, where x.xi is the version number of the ISE tools. ISE may come up with the last project opened by the tool but a new project needs to be started for the tutorial. To create a new project, click on the menu File->New Project. This will bring up a small dialog box with information about the new project. In the "Project Name" box, type sequence, the name we will use for the StateCAD tutorial. Now, select an appropriate location for all of the project files in the "Project Location" box, preferably use some space on your M: drive. The "Device" we are going to use is the Spartan-2 with the "Device Type" being the xc2s200-5pq208. The only synthesis tool available for this type of FPGA is XST.
Step 2 - Create the Sequence State Diagram using StateCAD
Click on menu Project->New Source. Select "State Diagram" from the left pane and name the file seq_sm (Figure 2).
Figure 2 - New
Source Window
Click "Next" and then "Finish". StateCAD will open with a blank State Diagram (Figure 3). In the event that StateCAD wants to start a tutorial, cancel out of all of the message boxes to get to a blank diagram.
Figure 3 - Blank
State Diagram
Click on the "Draw State Machines" button on the toolbar. This will open the State Machine Wizard (Figure 4). Select a geometric diagram with 4 states and then click "Next".
Figure 4 - State Machine Wizard
Since the Spartan-XL FPGA has only asynchronous reset capability, select asynchronous as the reset mode (Figure 5). Click on "Next".
Figure 5 - Reset
Mode
To setup the transitions from one state to another, select both the "Next" and "Previous" options in the "Setup Transitions" window (Figure 5). Click on "Finish" to create the state diagram.
Figure 6 - Setup
Transitions
Now that the template state diagram has been created, it still needs to be placed onto the blank diagram window. To place the diagram created from the wizard, left-click anywhere on the blank diagram; an inch from the top-left corner is a good place (Figure 7).
Figure 7 - Placed
Template State Diagram
Now that the basic diagram is in place, we need to add/remove/modify the current transitions to obtain the correct state diagram for the sequence generator. Left-click on one of the two boxes of the transition arrow State0-->State1. This will bring up the "Edit Conditions" dialog box (Figure 8). Add the condition MODE = '1' in the "Conditions" box.
Figure 8 - Edit
Conditions Dialog
This condition will make the transition State0-->State1 occur when MODE is true or '1'. To assign the correct output of the transition, click on the "Output Wizard" button. Select "Constant" from the upper left box, type 2 in the "CONSTANT" box, type DOUT in the "DOUT" box, and set the "Data path width" to 2 (Figure 9). Click on "OK".
Figure 9 - Output
Wizard
The "Edit Conditions" window will now look like Figure 10. Click on "OK".
Figure 10 - Completed
Transition
The state diagram will now look like Figure 11.
Figure 11 - Modified
State Diagram 1
At some point you will need to resize and move the transition text so as to make it more readable and organized. This can be done by holding down the left mouse button and moving the mouse accordingly.
Modify the following state transitions, as performed above, to correct the state diagram template:
State1-->State0
Condition: MODE = '1'
Output: DOUT = 0;
State2-->State1
Condition: MODE = '0'
Output: DOUT = 1;
The state diagram should now look like Figure 12.
Figure 12 - Modified
State Diagram 2
Since not all of the transitions from the template are needed, they need to be deleted by left-clicking on the transition line and pressing the delete key. The following state transitions need to be deleted:
State0-->State3
State2-->State1
State2-->State3
State3-->State2
The state diagram should now look like Figure 13.
Figure 13 - Modified
State Diagram 3
We now need to draw the state transitions State0-->State2, State1-->State3, State2-->State0, as well as apply the conditions and outputs of each. To do this, press the button with the blue curved line on the left toolbar. Left-click twice on State0 to start the beginning on the transition, indicated by a red box, and once more at State2 to end the transition. Do the same from State1 to State3 and State2 to State0. The state diagram should now look like Figure 14.
Figure 14 - Modified
State Diagram 4
Finish the diagram by applying the following conditions and outputs for each transition:
State0-->State2
Condition: MODE = '0'
Output: DOUT = 2;
State1-->State3
Condition: MODE = '0'
Output: DOUT = 3;
State
2-->State0
Condition: MODE = '1
Output: DOUT = 0;
The final state diagram is shown in Figure 15.
Figure 15 - Final
State Diagram
Now that the diagram is completed, we need to export the VHDL code. Click on the "Generate HDL" button from the top toolbar. A window will appear with the output, DOUT in the list of possible outputs to be registered. Since we do not want registered outputs, click on the "Cancel" button. A successful result window, shown in Figure 16, will appear. Click the "Close" button and exit StateCAD.
Figure 16 - Results
Window
Step 3 - Copy and Add the Tutorial Source Files
Copy the following files into your project root project directory (under the sequence directory)
intclk.vhd
sequence.vhd
sequence_tb.udo
Once these are copied to you project directory, add SEQ_SM.VHD (the exported VHDL code from StateCAD), intclk.vhd (the internal clock from the ripple project) and sequence.vhd (the top-level VHDL instatiation of INTCLK and SEQ_SM) to your project.
Step 4 - Generating the Testbench Using HDL Bencher
HDL Bencher is a companion tool for the Xilinx Foundation ISE design package. It is used to generate an HDL file to place the designed circuit under tested conditions, for both functional and timing simulation purposes. For this tutorial, we are only going to perform a functional simulation on sequence.vhd (the top-level design), and our testbench file will test all possibilities.
To start the HDL Bencher tool, double-click on the entry "Launch HDL Bencher Tool" under the "Design Entry Tools" in the "Processes For Current Source" window; please note that you must have the sequence.vhd file highlighted in the "Source In Project" window. The window called "Initialize Timing" will appear (Figure 17). This is used to derived the desired timing scheme used for the testbench. Change the "Time Scale" to ms (milliseconds), set the "Check Outputs" box to 500, and the "Assign Inputs" to 500.
Figure 17 - Initialize
Timing Window
In this example, the testbench can be created in any variety of ways, just so long as design is completely tested. Figure 18 shows one such possible waveform.
Figure 18 - Finished
Testbench Waveform
Click on "Export Testbench" button on the toolbar to take a look at the VHDL code. Save the waveform by clicking on the menu File->Save Waveform. Exit HDL Bencher and return to the Project Manager.
Step 5 - Functional Simulation of the Design
Now that the testbench for the design has been created, it still needs to be added to the project. To add this VHDL file, click on the menu Project->Add Source and select the file named SEQUENCE_TB.VHD, located in your project directory. A window will appear indicating that the file has an ambiguous suffix type; select "VHDL Test Bench" and click "Ok". Now that the testbench has been added, we need to set up the Modelsim environment to run properly run the simulation. Make sure that the sequence_tb.vhd file is highlighted in the "Source In Project" window and then right-click on the "Simulate Functional VHDL Model" selection in the "Processes for Current Source" window, and select "Properties" from the popup menu. You should see a dialog box entitled "Process Properties". Change the simulation time in the box "Simulation Run Time" to the length of your testbench. Click on the other tab at the top of the box to get to "Display Options" properties. Check all of the boxes and click on the button "OK". Again, make sure that the sequence_tb.vhd file is highlighted in the "Source In Project" window and then double-click on the "Simulate Functional VHDL Model" selection in the "Processes for Current Source" window. This will start Modelsim and run the testbench simulation.
Step 6 - Design Implementation
We first need to enter the desired location (pin) constraints for the design to properly fit the capabilities of the Spartan-XL board. In the past, we have used the GUI Xilinx Constraints Editor but this time we will enter them by hand in the User Constraint File (UCF). To open the UCF file, make sure the sequence.vhd file is highlighted in the "Sources In Project" window, click on the "Design Entry Tools" in the "Processes for Current Design" window, then click on "User Constraints" and finally double-click on "Edit UCF File". Once the file is opened in notepad, enter the following lines of text to apply location (LOC) constraints:
NET MODE LOC = P16;
NET RESET LOC = P18;
NET DOUT<0> LOC = P44;
NET DOUT<1> LOC = P46;
Click on the menu File->Save and close out notepad.
Before you implement the design, open up the source file "intclk.vhd" and fix the file for synthesis. Uncomment the OSC4 component and comment out the simulated clock line. Save the file and click on the sequence.vhd file.
To run the full implementation, from Translate to Bitstream Generation, double-click on the "Create Programming File" section under the "Processes For Current Source" window. You should see a lot of messages getting written into "Console" window. Ignore any warnings.
Step 7 - Download to the Board
Conclusion
During this tutorial you learned the StateCAD and VHDL design flow for the ISE tools including testbench generation, functional simulation, implementation, and downloading to the Spartan-XL boards. Now that the basics of the ISE tools have been explored, use the help files for each tool to learn more about the capabilities to enhance your designs.
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Modified from version written by Brian Foulds of Michigan State University