Index of /~bai/EGC221

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[PARENTDIR]Parent Directory   -  
[   ]Xilinx_ise14_tutoria..>2018-02-22 13:53 4.7M 
[   ]DE0_CV_User_Manual_1..>2016-09-07 14:02 4.5M 
[   ]Lab 3 - Combinationa..>2016-09-07 14:28 3.6M 
[   ]Tutorial on Quartus_..>2017-10-04 11:30 2.8M 
[   ]Tutorial on Quartus_..>2018-02-13 12:45 2.5M 
[   ]Quartus_II_Introduct..>2016-09-07 14:02 2.3M 
[   ]Quartus_II_Introduct..>2016-09-07 14:02 2.0M 
[   ]ISE Tutorial_Verilog..>2018-02-22 13:53 1.6M 
[   ]ISE Tutorial 14.1.pdf 2018-02-22 13:53 1.6M 
[   ]ISE Tutorial.pdf 2018-02-22 13:53 1.3M 
[   ]ISE Tutorial 10.1.pdf 2018-02-22 13:53 1.2M 
[   ]ISE Download Tutoria..>2018-02-22 13:53 1.2M 
[   ]ISIM Simulator_veril..>2018-02-22 13:53 1.0M 
[   ]ISE Simulator 14.1.pdf 2018-02-22 13:53 1.0M 
[   ]Lab 2 - Basic Logic ..>2016-09-07 14:28 1.0M 
[   ]Lab 1 - Basic Logic ..>2016-09-07 14:28 1.0M 
[   ]Lecture Notes 9-13-2..>2018-09-13 17:17 968K 
[   ]ewb.pdf 2018-02-22 13:53 809K 
[   ]Lab 1 - Basic Logic ..>2016-09-07 14:28 794K 
[   ]74160.pdf 2018-02-22 13:53 758K 
[   ]Xilinx Verilog Tutor..>2018-02-22 13:53 707K 
[   ]7 - Design Using Ver..>2018-04-16 16:14 662K 
[   ]ISE Simulator.pdf 2018-02-22 13:53 635K 
[   ]Download Tutorial NE..>2018-02-22 13:53 633K 
[   ]ISE Download Tutoria..>2018-02-22 13:53 594K 
[   ]xilinx_tutorial.pdf 2018-02-22 13:53 588K 
[   ]Lab7-Lecture Notes.pdf 2018-10-30 09:22 570K 
[   ]Xilinx VHDL Tutorial..>2018-02-22 13:53 563K 
[   ]ModelSim tutorial.pdf 2018-02-22 13:53 539K 
[   ]Lab5 -Lecture Notes.pdf2018-10-16 15:10 499K 
[   ]Lab 9 - Sequential D..>2017-11-28 11:17 467K 
[   ]Lab 2-Lecture Notes.pdf2018-09-11 11:47 462K 
[   ]Getting_Started_with..>2016-09-07 14:02 437K 
[   ]ISE Simulator 10.1.pdf 2018-02-22 13:53 417K 
[   ]Download Tutorial.pdf 2018-02-22 13:53 386K 
[   ]Model Sim Tutorial.pdf 2018-02-22 13:53 383K 
[   ]Lab 5 - Arithmetic C..>2017-10-04 11:30 373K 
[   ]Lab8-Lecture Notes.pdf 2018-11-13 09:22 370K 
[   ]Lab4 -Lecture Notes.pdf2018-09-25 12:56 347K 
[   ]syl_Digital Logic La..>2018-08-25 18:05 346K 
[   ]PALCE16V8.pdf 2018-02-22 13:53 345K 
[   ]16v8.pdf 2018-02-22 13:53 345K 
[   ]ModelSim tutorial 8.pdf2018-02-22 13:53 344K 
[   ]Lab9-Lecture Notes.pdf 2018-11-20 09:43 331K 
[   ]State Diagram Tutori..>2018-02-22 13:53 318K 
[   ]Lab 4 - Combinationa..>2018-10-16 15:07 314K 
[   ]Lab 1-Lecture Notes.pdf2018-09-06 15:12 311K 
[   ]Xilinx VHDL Tutorial..>2018-02-22 13:53 271K 
[   ]warptut.pdf 2018-02-22 13:53 252K 
[   ]State Diagram Tutori..>2018-02-22 13:53 246K 
[   ]Lab 2 - Basic Logic ..>2016-09-07 14:28 232K 
[   ]Lab6.pdf 2018-02-22 13:53 227K 
[   ]Xilinx VHDL Tutorial..>2018-02-22 13:53 213K 
[   ]badTalk.pdf 2018-11-27 11:48 210K 
[   ]Lab6 -Lecture Notes.pdf2018-10-23 11:43 208K 
[   ]Lab 7 - Arithmetic L..>2017-04-04 11:39 201K 
[   ]State Diagram Tutori..>2018-02-22 13:53 200K 
[   ]Lab 8 - Arithmetic L..>2017-04-04 11:53 197K 
[   ]ch03_vhdl.pdf 2018-02-22 13:53 192K 
[   ]Verilog-Tutorial.pdf 2018-02-22 13:53 174K 
[   ]Lab 6 - Hierarchical..>2017-10-24 15:02 174K 
[   ]syl_digital_lab_fall..>2018-02-22 13:53 169K 
[   ]Lab3 -Lecture Notes.pdf2018-09-25 12:56 169K 
[   ]Lab8.pdf 2018-02-22 13:53 166K 
[   ]syl_digital_lab_spri..>2018-02-22 13:53 162K 
[   ]Verilog tutorial.pdf 2018-02-22 13:53 147K 
[   ]lab2.pdf 2018-02-22 13:53 141K 
[   ]Lab 3 - Combinationa..>2016-09-07 14:28 141K 
[   ]Lab3N.pdf 2018-02-22 13:53 137K 
[   ]Some hints.pdf 2018-02-22 13:53 134K 
[   ]Guide to final pres..>2017-05-02 09:22 133K 
[   ]Lab4.pdf 2018-02-22 13:53 127K 
[   ]Lab 9 - Sequential D..>2017-11-28 11:17 123K 
[   ]PARTS.doc 2018-02-22 13:53 118K 
[   ]Lab5.pdf 2018-02-22 13:53 108K 
[   ]Lab 4 - Combinationa..>2018-10-16 15:07 102K 
[   ]Interconnect Table -..>2018-02-22 13:53 97K 
[   ]Lab9.pdf 2018-02-22 13:53 84K 
[   ]Some suggestion to ..>2018-02-22 13:53 81K 
[   ]Lab 5 - Arithmetic C..>2017-10-04 11:30 74K 
[   ]digital_symbols.doc 2018-02-22 13:53 74K 
[   ]syl_Digital Logic La..>2018-01-30 10:52 70K 
[   ]sn74ls83.pdf 2018-02-22 13:53 69K 
[   ]Lab7.pdf 2018-02-22 13:53 67K 
[   ]Lab 7 - Arithmetic L..>2017-04-04 11:39 63K 
[   ]Interconnect Table -..>2018-02-22 13:53 61K 
[   ]Seq_desg_main.pdf 2018-02-22 13:53 60K 
[   ]Lab11.pdf 2018-02-22 13:53 58K 
[   ]Lab10.pdf 2018-02-22 13:53 58K 
[   ]Lab 8 - Arithmetic L..>2017-04-04 11:53 57K 
[TXT]ISE State EditorTut..>2018-02-22 13:53 53K 
[TXT]grade2.html 2018-02-22 13:53 52K 
[   ]Lab 6 - Hierarchical..>2017-10-24 15:02 48K 
[   ]HW2_fall 2018.pdf 2018-09-13 17:28 39K 
[TXT]grade.html 2018-02-22 13:53 38K 
[   ]Lab1.pdf 2018-02-22 13:53 37K 
[TXT]EE411 ISE Tutorial 2018-02-22 13:53 31K 
[TXT]Adder Using VHDL.htm 2018-02-22 13:53 31K 
[   ]Lab Report Template.doc2018-02-22 13:53 30K 
[TXT]syl_digital_lab.htm 2018-02-22 13:53 29K 
[   ]DEO_CV.qsf 2016-09-07 14:02 27K 
[TXT]EGC208_fall.htm 2018-02-22 13:53 25K 
[TXT]EGC208_spring.htm 2018-02-22 13:53 25K 
[TXT]PLD_Tutorial.html 2018-02-22 13:53 25K 
[   ]VDHL ALU Tutorial.pdf 2018-02-22 13:53 24K 
[   ]lab3.pdf 2018-02-22 13:53 23K 
[TXT]EGC221_fall.html 2018-11-27 11:45 22K 
[TXT]EGC221_spring.html 2018-04-16 13:47 22K 
[TXT]Xilinx Foundation St..>2018-02-22 13:53 22K 
[TXT]common_mistake.html 2018-02-22 13:53 14K 
[TXT]ewb.html 2018-02-22 13:53 12K 
[   ]jed_down.pdf 2018-02-22 13:53 9.9K 
[TXT]lab5a_old.html 2018-02-22 13:53 9.0K 
[TXT]lab5a.html 2018-02-22 13:53 9.0K 
[TXT]lab4_old.html 2018-02-22 13:53 8.3K 
[TXT]lab4.html 2018-02-22 13:53 8.3K 
[TXT]lab6.htm 2018-02-22 13:53 8.1K 
[TXT]lab3.htm 2018-02-22 13:53 7.9K 
[TXT]lab4.htm 2018-02-22 13:53 7.8K 
[TXT]lab8b_old.html 2018-02-22 13:53 7.5K 
[TXT]lab8b.html 2018-02-22 13:53 7.5K 
[TXT]lab1.html 2018-02-22 13:53 6.2K 
[TXT]lab5b.htm 2018-02-22 13:53 6.2K 
[TXT]lab5b_old.html 2018-02-22 13:53 6.1K 
[TXT]lab5b.html 2018-02-22 13:53 6.1K 
[TXT]Lab6a.htm 2018-02-22 13:53 5.7K 
[TXT]lab6a_old.html 2018-02-22 13:53 5.7K 
[TXT]lab6a.html 2018-02-22 13:53 5.7K 
[TXT]syl_40208.html 2018-02-22 13:53 5.0K 
[TXT]lab5_old.html 2018-02-22 13:53 3.9K 
[TXT]lab5.html 2018-02-22 13:53 3.9K 
[TXT]lab9b_old.html 2018-02-22 13:53 3.9K 
[TXT]lab9b.html 2018-02-22 13:53 3.9K 
[TXT]lab7_old.html 2018-02-22 13:53 2.3K 
[TXT]lab7.html 2018-02-22 13:53 2.3K 
[TXT]lab8_old.html 2018-02-22 13:53 1.8K 
[TXT]lab8.html 2018-02-22 13:53 1.8K 
[TXT]lab3_old.html 2018-02-22 13:53 1.5K 
[TXT]lab6_old.html 2018-02-22 13:53 1.5K 
[TXT]lab6.html 2018-02-22 13:53 1.5K 
[TXT]lab3.html 2018-02-22 13:53 1.5K 
[TXT]lab9_old.html 2018-02-22 13:53 1.4K 
[TXT]lab9.html 2018-02-22 13:53 1.4K 
[TXT]lab2.htm 2018-02-22 13:53 1.4K 
[TXT]lab2_old.html 2018-02-22 13:53 1.2K 
[TXT]lab2.html 2018-02-22 13:53 1.2K 
[TXT]lab5.htm 2018-02-22 13:53 1.1K 
[TXT]lab4a_old.html 2018-02-22 13:53 1.0K 
[TXT]lab4a.html 2018-02-22 13:53 1.0K 
[TXT]lab1_old.html 2018-02-22 13:53 1.0K 
[TXT]lab3a_old.html 2018-02-22 13:53 951  
[TXT]lab3a.html 2018-02-22 13:53 924  
[TXT]lab3a.htm 2018-02-22 13:53 924  
[TXT]lab4b_old.html 2018-02-22 13:53 902  
[TXT]lab4b.html 2018-02-22 13:53 902  
[TXT]lcdf_vhdl.func_prims..>2018-02-22 13:53 30  
[DIR]Xilinx Foundation St..>2018-02-22 13:53 -  
[DIR]Adder Using VHDL_files/2018-02-22 13:53 -