Lecture Date |
Lecture Note |
Watch Lecture Video
on Blackboard |
Additional Activity |
Lecture Notes |
|
Syllabus |
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5/14/2018 |
1-Number systems |
Lectures 1 & 2 |
Read text Chaper 1, Try Problems 1 |
Class Notes 1/25/18 |
5/15/2018 |
1-Number systems |
Lectures 3 & 4 |
Read text Chaper 1, Try Problems 2 |
Class Notes 1/29/18 |
5/16/2018 |
1-Number systems |
Lectures 5 &6 |
Read text Chaper 1, Try Problems 3 |
Class Notes 2/1/18 |
5/17/2018 |
2 - Boolean Logic |
Lectures 7 & 8 |
Read text Chapter 2, see sample operations, Try Problem 4 |
Class Notes 2/5/18 |
5/18/2018 |
Lab 1 & 2 |
|
Basic Logic Gate Simulation (Word) (PDF)
Basic Logic Gate Physical Verification (Word) (PDF) |
|
5/21/2018 |
3 - Boolean Logic Functions |
Lectures 9 & 10 |
Read text Chapter 2, Try Problem 5 |
Class Notes 2/8/2018 |
5/22/2018 |
3 - Boolean Logic Functions |
Lectures 11 & 12 |
Read text Chapter 2, Try Problem 6 |
Class Notes 2/12/2018 |
5/23/2018 |
3 - Boolean Logic Functions |
Lectures 13 & 14 |
Read text Chapter 2,Try Problem 7 |
Class Notes 2/15/2018 |
5/24/2018 |
4-Simplification Using K-Map |
Lectures 15 & 16 |
Read Text Chapter 3,Try Problem 8 |
Class Notes 2/22/2018 |
5/25/2018 |
Lab 3 &4 |
|
Combinational Logic Circuits (Word) (PDF)
Combinational Logic Circuit Reduction (Word) (PDF) |
|
5/28/2018 |
4-Simplification Using K-Map |
Lectures 17 & 18 |
Read Text Chapter 3,Try Problem 9 |
Class Notes 2/26/2018 |
5/29/2018 |
5-Design of Combinational Circuits |
Lectures 19 & 20 |
Read Text Chapter 3,Try Problem 10 |
Class Notes 3/1/2018 |
5/30/2018 |
Test 1 |
|
Practice Problems |
Test 1 Solution |
5/31/2018 |
5-Design of Combinational Circuits |
Lectures 21& 22 |
Read Text Chapter 3, Try Problem 11 |
|
6/1/2018 |
Lab 5 |
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6/4/2018 |
Design of Decoders |
Lectures 23 & 24 |
Read Text Chapter 3, Try Problem 12 |
Class Notes 3/12/2018 |
6/5/2018 |
Design of Encoder / Mux/ DeMux |
Lectures 25 & 26 |
Read Text Chapter 3, Try Problem 13 |
Class Notes 3/15/2018 |
6/6/2018 |
6- Programmable Logic Devices |
Lectures 27 & 28 |
Try Problem 14 |
Class Notes 3/26/2018 |
6/8/2018 |
Lab 6 |
|
Arithmetic Circuits Using Altera Quartus II (Word) (PDF) |
|
6/13/2018 |
7- Design Using Verilog |
Lectures 29 & 30 |
Read Text Chapter 4, Try Problem 15 |
Class Notes 3/29/2018 |
6/14/2018 |
7- Design Using Verilog
8- Latches |
Lectures 31 & 32 |
Read Text Chapter 5, Try Problem 16 |
Class Notes 4/2/2018 |
6/15/2018 |
Lab 7 |
|
Arithmetic Logic Unit (ALU) Schematic Implementation (Word) (PDF) |
|
6/18/2018 |
8- Flip-flops and Ripple Counters |
Lectures 33 & 34 |
Read text Chaper 5 & Try Problem 17 |
Class Notes 4/5/2018 |
6/19/2018 |
8- Asynchronous and Synchronous Circuits |
Lectures 35 & 36 |
Read text Chaper 5 & Try Problem 18 |
Class Notes 4/9/2018 |
6/20/2018 |
8- Analysis of Sequential Circuits |
Lectures 37 & 38 |
Read text Chaper 5 & Try Problem 19 |
Class Notes 4/12/2018 |
6/21/2018 |
Test 2 |
|
Practice Problems |
Test 2 Solution |
6/22/2018 |
Lab 8 |
|
Arithmetic Logic Unit (ALU) Verilog Implementation (Word) (PDF) |
|
6/25/2018 |
8- Design of Sequential Circuits |
Lectures 39 & 40 |
Read Text Chapter 5, Try Problem 20 |
Class Notes 4/19/2018 |
6/26/2018 |
8- Sequential Circuits |
|
Read Text Chapter 5, Try Problem 20 |
Class Notes 4/23/2018 |
6/27/2018 |
8- Verilog in Sequential Circuits |
Lectures 41 & 42 |
Read Text Chapter 5, Try Problem 21 |
Class Notes 4/26/2018 |
6/28/2018 |
8- Design of Finite State Machines |
Lectures 43 & 44 |
Try Problem 22 |
Class Notes 4/30/2018 |
6/29/2018 |
Lab 9 |
|
Sequential Design Using Verilog (Word) (PDF) |
|
7/2/2018 |
8- Design of a Controller |
Lectures 45 |
Read Text Chapter 5, Try Problem 23 |
Class Notes 5/3/2018 |
7/3/2018 |
Final Exam |
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Practice Problems |
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